Documents | CMU-NCA Lab

BOOKS & BOOK CHAPTERS (B)
1. Cortical Columns Computing Systems: Microarchitecture Model, Functional Building Blocks, and Design Framework," Harideep Nair, PhD Dissertation, Oct. 2024.
2. Cortical Columns Computing Systems: Microarchitecture Model, Functional Building Blocks, and Design Tools," John Paul Shen and Harideep Nair, Neuromorphic Computing, Ch. 8, IntechOpen, 15 Nov. 2023.
3. "Space-Time Computing with Temporal Neural Networks," James E. Smith, Synthesis Lectures on Computer Architecture 2017.

PUBLICATIONS [P]
1. "Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs," Prabhu Vellaisamy, Harideep Nair, Thomas Kang, Yichen Ni, Haoynag Fan, Bin Qi, Jeff Chen, Shawn Blanton, and John Paul Shen, DATE 2025.
2. "Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference," Harideep Nair, Prabhu Vellaisamy, Tsung-Han Lin, Perry Wang, Shawn Blanton, and John Paul Shen, VLSI-SoC 2024.
3. "Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators," Prabhu Vellaisamy, Harideep Nair, Di Wu, Shawn Blanton, and John Paul Shen, ISVLSI 2024.
4. "Realtime Person Identification via Gait Analysis," Shanmuga Venkatachalam, Harideep Nair, Prabhu Vellaisamy, Yongqi Zhou, Ziad Youssfi, and John Paul Shen, ICONS 2024.
5. "NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors," Harideep Nair, William Leyman, Agastya Sampath, Quinn Jacobson, and John Paul Shen, NICE 2024.
6. "TNN-CIM: An In-SRAM CMOS Implementation of TNN-Based Synaptic Arrays with STDP Learning," Harideep Nair, David Barajas-Jasso, Quinn Jacobson, and John Paul Shen, AICAS 2024.
7. "TNNGen: Automated Design of Neuromorphic Sensory Processing Units for Time-Series Clustering," Prabhu Vellaisamy, Harideep Nair, Vamsikrishna Ratnakaram, Dhruv Gupta, and John Paul Shen, Accepted in ISCAS 2024 and Invited for Publication in TCAS-II: Express Briefs.
8. "tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit," Prabhu Vellaisamy, Harideep Nair, Joseph Finn, Manav Trivedi, Albert Chen, Anna Li, Tsung-Han Lin, Perry Wang, Shawn Blanton, and John Paul Shen, ISVLSI 2023.
9. "tuGEMM: Area-Power-Efficient Temporal Unary GEMM Architecture for Low Resolution Edge AI," Harideep Nair, Prabhu Vellaisamy, Albert Chen, Joseph Finn, Anna Li, Manav Trivedi, and John Paul Shen, ISCAS 2023.
10. "SemNet: Learning Semantic Attributes for Human Activity Recognition with Deep Belief Networks," Shanmuga Venkatachalam, Harideep Nair, Ming Zeng, Cathy Tan, Ole J. Mengshoel, and John Paul Shen, Frontiers in Big Data 2022
11. "TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs," Harideep Nair, Prabhu Vellaisamy, Santha Bhasuthkar, & John Paul Shen, ISVLSI 2022.
12. "Unsupervised Clustering of Time Series Signals Using Neuromorphic Energy-Efficient Temporal Neural Networks," Shreyas Chaudhari, Harideep Nair, Jose M.F. Moura, & John Paul Shen, ICASSP 2021.
13. "A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks," Harideep Nair, John Paul Shen, & James E. Smith, ISVLSI 2021.
14. "Space-Time Algebra: A Model for Neocortical Computation," James E. Smith, ISCA 2018.

PRESENTATIONS & POSTERS [PR]
1. "Cortical Columns Computing Systems (C3S): Towards a Silicon Neocortex for AI Compute," Harideep Nair and John Paul Shen, IBM IEEE CAS/EDS AI Compute Symposium 2023.
2. "Towards a Design Framework for TNN-Based Neuromorphic Sensory Processing Units," Prabhu Vellaisamy and John Paul Shen, The 4th Young Architect Workshop (YArch'22), at ASPLOS 2022. https://web.mit.edu/yarch2022/
3. "A Road Map for Reverse-Architecting the Brain's Neocortex," James E. Smith, FCRC Keynote 2019.

RESEARCH NOTES [RN]
1. "Neuromorphic Online Clustering and Classification," James E. Smith, 10/26/2023.
2. "A Macrocolumn Architecture Implemented with Spiking Neurons," James E. Smith, 2/9/2023.
3. "(Newtonian) Space-Time Algebra," James E. Smith, 6/15/2019.

BOOKS & BOOK CHAPTERS (B)

Cortical Columns Computing Systems: Microarchitecture Model, Functional Building Blocks, and Design Framework," Harideep Nair, PhD Dissertation, Oct. 2024.

Cortical Columns Computing Systems: Microarchitecture Model, Functional Building Blocks, and Design Tools," John Paul Shen and Harideep Nair, Neuromorphic Computing, Ch. 8, IntechOpen, 15 Nov. 2023.

​"Space-Time Computing with Temporal Neural Networks,"​​ James E. Smith, Synthesis Lectures on Computer Architecture 2017.

​​​

PUBLICATIONS [P]

"Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs," Prabhu Vellaisamy, Harideep Nair, Thomas Kang, Yichen Ni, Haoynag Fan, Bin Qi, Jeff Chen, Shawn Blanton, and John Paul Shen, DATE 2025.

"Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference," Harideep Nair, Prabhu Vellaisamy, Tsung-Han Lin, Perry Wang, Shawn Blanton, and John Paul Shen, VLSI-SoC 2024.

"Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators​," Prabhu Vellaisamy, Harideep Nair, Di Wu, Shawn Blanton, and John Paul Shen, ISVLSI 2024.

"Realtime Person Identification via Gait Analysis," Shanmuga Venkatachalam, Harideep Nair, Prabhu Vellaisamy, Yongqi Zhou, Ziad Youssfi, and John Paul Shen, ICONS 2024.

"NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors," Harideep Nair, William Leyman, Agastya Sampath, Quinn Jacobson, and John Paul Shen, NICE 2024.

"TNN-CIM: An In-SRAM CMOS Implementation of TNN-Based Synaptic Arrays with STDP Learning," Harideep Nair, David Barajas-Jasso, Quinn Jacobson, and John Paul Shen, AICAS 2024.

"TNNGen: Automated Design of Neuromorphic Sensory Processing Units for Time-Series Clustering," Prabhu Vellaisamy, Harideep Nair, Vamsikrishna Ratnakaram, Dhruv Gupta, and John Paul Shen, Accepted in ISCAS 2024 and Invited for Publication in TCAS-II: Express Briefs.

"tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit," Prabhu Vellaisamy, Harideep Nair, Joseph Finn, Manav Trivedi, Albert Chen, Anna Li, Tsung-Han Lin, Perry Wang, Shawn Blanton, and John Paul Shen, ISVLSI 2023.

"tuGEMM: Area-Power-Efficient Temporal Unary GEMM Architecture for Low Resolution Edge AI," Harideep Nair, Prabhu Vellaisamy, Albert Chen, Joseph Finn, Anna Li, Manav Trivedi, and John Paul Shen, ISCAS 2023.

"SemNet: Learning Semantic Attributes for Human Activity Recognition with Deep Belief Networks," Shanmuga Venkatachalam, Harideep Nair, Ming Zeng, Cathy Tan, Ole J. Mengshoel, and John Paul Shen, Frontiers in Big Data 2022

"TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs," Harideep Nair, Prabhu Vellaisamy, Santha Bhasuthkar, & John Paul Shen, ISVLSI 2022.

"Unsupervised Clustering of Time Series Signals Using Neuromorphic Energy-Efficient Temporal Neural Networks," Shreyas Chaudhari, Harideep Nair, Jose M.F. Moura, & John Paul Shen, ICASSP 2021.

"A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks," Harideep Nair, John Paul Shen, & James E. Smith, ISVLSI 2021.

"Space-Time Algebra: A Model for Neocortical Computation," James E. Smith, ISCA 2018.

​​

PRESENTATIONS & POSTERS [PR]

"Cortical Columns Computing Systems (C3S): Towards a Silicon Neocortex for AI Compute," Harideep Nair and John Paul Shen, IBM IEEE CAS/EDS AI Compute Symposium 2023.

"Towards a Design Framework for TNN-Based Neuromorphic Sensory Processing Units," Prabhu Vellaisamy and John Paul Shen, The 4th Young Architect Workshop (YArch'22), at ASPLOS 2022. https://web.mit.edu/yarch2022/

"A Road Map for Reverse-Architecting the Brain's Neocortex," James E. Smith, FCRC Keynote 2019.

​

RESEARCH NOTES [RN]

"Neuromorphic Online Clustering and Classification," James E. Smith, 10/26/2023.

"A Macrocolumn Architecture Implemented with Spiking Neurons," James E. Smith, 2/9/2023.

"(Newtonian) Space-Time Algebra," James E. Smith, 6/15/2019.

​

"Space-Time Computing with Temporal Neural Networks," James E. Smith, Synthesis Lectures on Computer Architecture 2017.

"Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators," Prabhu Vellaisamy, Harideep Nair, Di Wu, Shawn Blanton, and John Paul Shen, ISVLSI 2024.